Die-Level Thinning for Flip-Chip Integration on Flexible Substrates

Die-level thinning, handling, and integration of singulated dies from multi-project wafers (MPW) are often used in research, early-stage development, prototyping flexible devices. There is a high demand for thin silicon devices several applications, such as electronics. To address this demand, we study novel post-processing method on two devices, an electrochemical impedance sensor, Complementary Metal Oxide Semiconductor (CMOS) die. Both drawn MPW batch, thinned at die-level after dicing singulation down to 60 µm. The were flip-chip bonded substrates hermetically sealed by techniques: thermosonic bonding Au stud bumps anisotropic conductive paste (ACP) bonding. performance the was assessed via functional tests compared original dies. Furthermore, long-term reliability sensors demonstrated be higher than conventional wire-bonded sensors.